View TA1384FNG_4134232.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TA1384FNG TOSHIBA BIPOLAR LINEAR INTEGRATED CIRCUIT SILICON MONOLITHIC
TA1384FNG
Mixer/Oscillator and PLL IC for TV/VCR Tuner
The TA1384FNG is a tuner IC for TV and VCR applications that integrates a PLL block and mixer, oscillator and IF amplifier on a single chip. The control data of the PLL block conforms to IC-bus formats. Small flat package: SSOP24 (0.65 mm pitch)
Features
Weight: 0.09 g (typ.) Vcc: 5Vtyp. Two-band mixer Two-band oscillator IF output driver Asymmetrical IF output IC bus format control 33-V high voltage tuning amplifier built-in Four-bit bandswitch drive transistor Frequency steps: 31.25 kHz, 50 kHz, 62.5 kHz (when a 4 MHz crystal is used) Four-programmable chip address Power on reset circuit Automatic changeover between 1/4 and 1/2 prescaler through data input Package: Pb-free
Power on reset status
Frequency step: 62.5 kHz Charge pump current: Low Counter data: ALL [ 0 ] Band driver: OFF Tuning amplifier: OFF (Charge pump = sink mode) Local oscillator and mixer: UHF mode Note 1: This device is sensitive to surge voltage and electrostatic discharge. Handle with care.
1
2004/11/24
TA1384FNG Block Diagram
GND3 24 X'tal 23 NF 22 Vt out 21 IF out 20 Vcc 19 GND2 18 UHF OSC2 17 UHF OSC1 16 VHF VHF VHF OSC-C1 OSC-C2 OSC-B1 14 13 15
DIVIDER 1/2 1/4
1/32 1/33 PHASE COMPARATOR
PROGRAMABLE DIVIDER B1 BAND SW UV
DATA INTERFACE
BAND DRIVER ADR B2
1 SCL
2 SDA
3 ADR
4 BS1
5 BS2
6 BS3
7 BS4
8 MIX out1
9 MIX out2
10 GND1
11 VHF in
12 UHF in
Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes.
Terminal Name
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SCL input SDA in/output ADR (address setting) Band 1 output (VHF mode) Band 2 output (VHF mode) Band 3 output (UHF or FMT) Band 4 output (UHF or FMT) Mixer output 1 Mixer output 2 GND 1 VHF RF input UHF RF input VHF oscillator -B1 VHF oscillator -C2 VHF oscillator -C1 UHF oscillator 1 UHF oscillator 1 GND 2 Vcc IF output Vt output NF Crystal input GND 3 Pin Name
2
2004/11/24
TA1384FNG Terminal Function
The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. Pin No. Pin Name. Function Interface
Vcc
1
SCL
Serial clock input pin
1
1k
GND
Vcc
2
SDA
Serial data input and output pin
2
22
1k
70k
GND
Vcc
150k 100k 1k
Address setting pin 3 ADR The address of the PLL block is set up using the voltage applied to this pin.
3
100
50k
GND
Vcc
4 5 6 7
BS1 ~ BS4
The output port of the band block can be set up using the control data. Bear in mind that drive current differs according to each band drive port..
50k
4 5 6 7
DATA I/F
GND
3
2004/11/24
TA1384FNG
Pin No. Pin Name. Function Interface
Mixer output pins 8 Mixer Output 9 A tank circuit is connected between the pins for tuning. Since these are open collector outputs, be sure to connect with a power supply through a load (resistance, coil).
8 9
GND
10 GND 1 Ground pin
11
RF signal input pin for the VHF band. 11 VHF RF Input Asymmetrical input type
GND
12
RF signal input pin for the UHF band. 12 UHF RF Input Asymmetrical input type
GND
14
15
13 14 15
Local oscillator for the VHF band VHF Oscillator The oscillator type is symmetrical amplifier
13
GND
16 17
16 UHF Oscillator 17
Local oscillator for the UHF band The oscillator type is symmetrical amplifier.
GND
4
2004/11/24
TA1384FNG
Pin No.
18 19
Pin Name.
GND 2 Vcc Ground pin
Function
Interface

Power supply pin
Vcc
IF signal output pin 20 IF Output Asymmetrical output type. Output impedance is about 75 .
20
GND
Vcc
21 Vt Output Be sure to connect a resistance (of about 33 k) between pin 21 and the 33-V external power supply for tuning. To prevent abnormal oscillation, connect between pin 21 and GND a capacity element that does not affect a PLL. 22 NF
50 21
50
50
GND 22
Vcc
Crystal oscillator input pin A 4-MHz crystal is used.
23
Crystal Input
23
GND
24 GND 3 Ground pin
5
2004/11/24
TA1384FNG Maximum Ratings
CHARACTERISTIC Vcc Tuning Amplifier Voltage Applied Bus Data Voltage Applied Pin for DC Voltage Applied Except for GND and the Above Pins RF Signal Input Level for Mixer Power Dissipation Operating Temperature Storage Temperature PIN No 19 21 1, 2 11,12 SYMBOL Vcc VBT SDA,SCL VIN fin PD Topr Tstg RATING 6 38 -0.3~6 -0.3~Vcc+0.3 120 890 (Note 3) -20~85 -55~150 UNIT V V V V dBuV mW
Note 2: The absolute maximum ratings of a semiconductor device are a set of specified parameter values that must not be exceeded during operation, even for an instant. If any of these rating are exceeded during operation, the electrical characteristics of the device may be irreparably altered, in which case the reliability and lifetime of the device can no longer be guaranteed. Moreover, any exceeding of the ratings during operation may cause breakdown, damage and/or degradation in other equipment. Applications using the device should be designed so that no maximum rating will ever be exceeded under any operating conditions. Before using, creating and/or producing designs, refer to and comply with the precautions and conditions set forth in this documents. Note 3: 50 x 50 x 1.6 mm, Cu 40% board used. When using the device at above Ta = 25, decrease the power dissipation by 7.2 mW for each increase of 1.
Operating Supply Voltage
Pin No. 19 SYMBOL Vcc MIN. 4.5 TYP. 5.0 MAX. 5.5 UNIT V
Electric Characteristics DC Characteristics
(Unless otherwise specified, Vcc = 5 V, Ta = 25)
CHARACTERISTICS Power Supply and Current Icc2 SYMBOL Icc1 1 UHF Bus data B4 = ON, (pin 7: Open) 52 65.5 79.5 TEST BAND CIRCUIT VHF TEST CONDITION Bus data B1 = ON, (pin 4: Open) MIN. 49 TYP. 62 MAX. 75 mA UNIT
6
2004/11/24
TA1384FNG MIX / OSC / IF Block
(Unless otherwise specified, Vcc = 5 V, Ta = 25)
CHARACTERISTICS SYMBOL TEST BAND CIRCUIT VHF Conversion Gain (see 1) CG 2 VHF UHF UHF VHF Noise Figure (see 2) VHF NF 3 UHF UHF VHF IF Output Power Level (see 3) VHF Ifp 2 UHF UHF VHF Conversion Gain Shift (see 4) VHF CGs 2 UHF UHF VHF Frequency Shift (The PLL is operating.) (see 5) not fB VHF 2 UHF UHF VHF 1% Cross Modulation (see 6) VHF CM 4 UHF UHF VHF 3 Inter Modulation for MOP block (see 7)
rd
TEST CONDITION (Notes 4 & 5) RF = 55.25 MHz -30 dBmWin RF = 367.25 MHz -30 dBmWin RF = 373.25 MHz -30 dBmWin RF = 801.25 MHz -30 dBmWin RF = 55.25 MHz RF = 367.25 MHz RF = 373.25 MHz RF = 801.25 MHz RF = 55.25 MHz RF = 367.25 MHz RF = 373.25 MHz RF = 801.25 MHz RF = 55.25 MHz -30 dBmWin RF = 367.25 MHz -30 dBmWin RF = 373.25 MHz -30 dBmWin RF = 801.25 MHz -30 dBmWin OSC = 101 MHz OSC = 413 MHz OSC = 419 MHz OSC = 847 MHz fd = 55.25 MHz -30 dBmWin fd = 367.25 MHz -30 dBmWin fd = 373.25 MHz -30 dBmWin fd = 801.25 MHz -30 dBmWin fd = 55.25 MHz -35 dBmWin fd = 367.25 MHz -35 dBmWin fd =3 73.25 MHz -35 dBmWin fd = 801.25 MHz -35 dBmWin fp = 83.25 MHz, fs = 87.75 MHz -30 dBmW input
MIN. 20.5 21.5 25.0 25.5 8.5 8.5 8.5 8.5 -
TYP. 23.5 24.5 28.0 28.5 11.0 10.0 8.0 8.0 10 10 10 10 100 300 200 800 88 84 83 81 74 70 62 61 62
MAX. 26.5 27.5 31.0 31.0 -
UNIT
dB
dB dBmW 0.5 0.5 0.5 0.5 kHz dBuV dB UHF UHF dB dB
VHF IM3 4
6ch beat (see 8)
B6
4
VHF
Note 4: IF output frequency: 45.75 MHz
Note 5: IF output load: 75
7
2004/11/24
TA1384FNG PLL / Band Block
(Unless otherwise specified, Vcc = 5 V, Ta = 25)
CHARACTERISTICS SYMBOL IBD-1 Band Port Drive Current IBD-2 IBD-3 IBD-4 Band Port Drive Maximum Current Band Port Drive Voltage Drop Tuning Amplifier Output Voltage (Close Loop) Tuning Amplifier Maximum Current Crystal Negative Resistance Crystal Operating Range Crystal External Input Level Ratio Setting Range Logic Input Low Voltage Logic Input High Voltage Logic Input Current (Low) Logic Input Current (High) Charge Pump Output Current ACK Output Voltage IBDmax VBDsat Vt out Ivt XtR Xo fin Xo extl N VBsL VBsH I BsL I BsH Ichg VACK 1 1 3 3 1 1 2 1 1 1 1 1 CP = 1 1 ISINK = 3 mA 1 TEST CIRCUIT TEST CONDITION Pin 4, maximum drive current Pin 5, maximum drive current Pin 6, maximum drive current Pin 7, maximum drive current Maximum drive current / 2 port ON With each port at maximum current drive. 1 port ON Isink = 1.5 mA VBT = 33 V 4-MHz crystal used Ref. freq. = 4 MHz input 15-bit counter SDA, SCL pin SDA, SCL pin SDA, SCL pin SDA, SCL pin CP = 0 0.3 1 1024 -0.3 2.7 -20 -10 40 190 0.15 2 4 400 55 250 MIN. TYP. MAX. 7 10 3 7 17 0.2 33 1.5 32767 1.5 Vcc +0.3 10 20 70 310 0.4 uA V mA V V mA k MHz mVp-p Ratio V V uA uA mA UNIT
The range of the crystal external input level (Xo extl) in the internal circuit configuration is 300 - 650 mVp-p (when a signal of 4 MHz is applied).
8
2004/11/24
TA1384FNG IC Bus Line Characteristic
CHARACTERISTICS SCL Clock Frequency Bus Free Time between a STOP and a START Condition Hold Time (Repeated) START Condition Low Period of the SCL Clock High Period of the SCL Clock Set-up Time for a Repeated START Condition Data Hold Time Data Set-up Time Rise Time of both SDA and SCL Signal Fall Time of both SDA and SCL Signals Set up Time for STOP Condition SYMBOL fscl tBUF tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tR tF tsU;STO TEST CONDITION MIN. 0 1.3 0.6 1.3 0.6 0.6 0 100 0.6 TYP. MAX. 400 0.9 300 300 UNIT kHz
s s s s s s s s s s
SDA tBUF tLOW tR tF tHD; STA
SCL
P
S
tHD; STA
tHD; DAT
tHIGH
tSU; DAT
tSU; STA Sr
tSU; STO
P
Figure 1: IC-bus data timing chart (falling edge timing)
Timing charts may be simplified for explanatory purposes.
9
2004/11/24
TA1384FNG Test Conditions
Conversion Gain (see 1) RF Input level = -30dBmW (untuned) Noise Figure (see 2) Noise figure meter used. Direct reading. (DSB) IF Output Power Level (see 3) Measure IF output level when it is maximum level. Conversion Gain Shift (see 4) The conversion gain shift is defined as a change in conversion gain when supply voltage varies from Vcc = 5 V to 4.5 V or from Vcc = 5 V to 5.5 V. Frequency Shift (the PLL is not operating) (see 5) The frequency shift is defined as a change in oscillator frequency when supply voltage varies from Vcc = 5 V to 4.5 V or from Vcc = 5 V to 5.5 V. 1% Cross Modulation (see 6) fd = fp : (fd input level = -30dBmW) fud = fp 12MHz, 100 kHz AM30% Input two signals, and increase the fud input level. Measure the fud input level when the suppression level reaches 56.5dB. 3rd Internal Modulation (see 7) fd = fp : (fd Input level = -35dBmW) fud = fp 1 MHz : (fud input level = -35dBmW) Input two signals, measure the suppression level. 6-ch beat (see 8) fp = 83.25MHz : (input level = -30 dBmW) fs = 87.75MHz : (input level = -30 dBmW) Input two signals, measure the suppression level of the IF / undesired signal. *Undesired signal = (fp + fs) - fosc = (83.25 + 87.75) - 129 = 42 MHz.
10
2004/11/24
TA1384FNG Description of PLL Block Operation
- IC bus control The TA1384FNG conforms to the IC-bus format. IC-bus mode enables two-way bus communications with Write Mode, which receives data, and Read Mode, which sends data. Write Mode and Read Mode are set using the last bit (R/W bit) of the address byte. If the last address bit is set to [0], Write Mode is selected; if it is set to [1], Read Mode is selected. Addresses can be set using the hardware bits, and four programmable addresses are available. With this setting, multiple frequency synthesizers can be used in the same IC-bus. The address for the hardware bit setting can be selected by applying voltage to the address setting pin (ADR: pin 3).An address is selected according to the set bits. If the correct address bytes are received, the serial data (SDA) line is "Low" during acknowledgment; when Write Mode is set, the serial data (SDA) line is "Low" during the next acknowledgment if the data byte is programmed. The IC is equipped with 1/2 and 1/4 built-in prescalers, and it is possible to change from one prescaler to the other using input data. When a frequency step of 62.5 kHz is selected, the 1/2 prescaler operates with a divider ratio of 1024 to 4095, and the 1/4 prescaler operates with a divider ratio of 4096 to 32767. When the frequency step selected is 31.25 kHz and 50 kHz, the 1/2 prescaler operates with a divider ratio of 1024 to 8191, and the 1/4 prescaler operates with a divider ratio of 8192 to 32767. In addition, even if the prescaler is changed, the data is calculated in the internal circuit and is processed so that the comparison frequency in each the frequency step does not change. For a frequency step of 62.5 kHz: 15.625 kHz comparison frequency For a frequency step of 50 kHz: 12.5 kHz comparison frequency For a frequency step of 31.25 kHz: 7.8125 kHz comparison frequency This IC incorporates a built-in power-on reset circuit for which a detection voltage of approximately 1.4 V has been set. When the Vcc is supplied, a delay or stoppage in a power supply voltage close to this detection voltage may cause the power-on reset circuit to malfunction, in which case there is a risk that some data may not be received even after the recommended voltage has been restored.
A) Write Mode (Setting Command)
When WRITE mode is set so that the different types of information may be received, byte 1 is used to specify the address data; byte 2 and byte 3, the frequency data; byte 4, function setting data such as the divider ratio setting; and byte 5, the output port data (bandswitch data). Data are latched and transferred one after the other in the case of byte 3, byte 4 and byte 5, while byte 2 and byte 3 are latched and transferred as a two-byte set (byte 2 + byte 3). Once a correct address is received and acknowledged, the data type is determined by whether the first bit of the next byte is set to [0] or [1]. [0] indicates frequency data, while [1] indicates function setting or output data. Until the IC-bus STOP CONDITION is detected, the additional data can be input without transmitting the address data again. (For example: Frequency sweep is possible with additional frequency data.) If data transmission is aborted, data programmed before the abort are valid.
BYTE 1
Hardware bit setting of byte 1 is possible using the address data. The hardware bit is set with the voltage applied to the address-setting pin (ADR: pin 3).
BYTE 2, BYTE 3
Byte 2 , byte 3 are stored in the 15-bit shift register with counter data for the frequency setting, and control the 15-bit programmable counter ratio. The program frequency can be calculated in the following formula: fosc = 4 x fr x N. fosc 4 fr N : Program frequency : Prescaler : Phase comparator reference frequency (step frequency) : Counter total divider ratio
fr is calculated using the crystal oscillator and the reference frequency divider ratio set in byte 4 (control byte): fr = crystal oscillator frequency / reference divider ratio. The reference frequency divider ratio can be set to 1/512, 1/320, and 1/256. When using a 4-MHz crystal oscillator, fr = 7.8125 kHz, 12.5 kHz, and 15.625 kHz. The step frequency is 31.25 kHz, 50.0 kHz, and 62.5 kHz.
11
2004/11/24
TA1384FNG BYTE 4
Byte 4 is a control byte used to set the different functions. Bit 2 (CP) and controls the output current of the charge-pump circuit. When bit 2 is set to [0], the output current is set to +55 A; when it is set to [1] , it is +250 A. Bit 3 (T2), bit 4 (T1), and bit 5 (T0) are used to set the phase comparator reference signal output and counter divider output in test mode. (For details of test mode, see the test mode setting table.) Bit 6 (Rsa) and bit 7 (Rsb) are used to set the crystal reference frequency divider ratio. (For details of the crystal reference frequency divider ratio, see the table for crystal reference frequency divider ratios.) Bit 8 (OS) is used to set the charge-pump driver amplifier output setting. When bit 8 is set to [0], the output is ON (the normal setting used); when it is set to [1], the output is OFF (charge pump is sink mode).
BYTE 5
Byte 5 is used to set the test mode and control the output ports (Band 1 ~ Band 4). When an output port is set to [0], it is OFF; when it is set to [1], it is ON. Bandswitch setting is also used to switch between the VHF and UHF bands. When the bandswitch data for either B1 or B2 is [1], VHF mode is effective. When the bandswitch data for both B1 and B2 is [0], UHF mode is effective. Set the following maximum values for currents to the bandswitch driver. Ensure also that the total band current is within 17 mA when two bands are operating at the same time. Band 1 (pin 4) output current: 7 mA (maximum) Band 2 (pin 5) output current: 10 mA (maximum) Band 3 (pin 6) output current: 3 mA (maximum) Band 4 (pin 7) output current: 7 mA (maximum)
B) READ MODE (Status Request)
When Read Mode is set, power-on reset operation status and phase comparator lock detector output status are output to the master device. Bit 1 (POR) indicates the power-on reset operation status. When the power supply of Vcc stops, this bit is set to [1]. The conditions for reset to [0] are that voltage supplied to Vcc is 3V or higher, that transmission is requested in READ MODE, and that the status is output. (When Vcc is turned on, bit 1 is also set to [1].) Bit 2 (FL) indicates the phase comparator lock status. When this is locked, [1] is output; when it is unlocked, [0] is output.
12
2004/11/24
TA1384FNG DATA FORMAT A) WRITE MODE
MSB 1 2 3 4 5 Address Byte Divider Byte 1 Divider Byte 2 Control Byte Band SW Byte 1 0 N7 1 X 1 N14 N6 CP X 0 N13 N5 T2 X 0 N12 N4 T1 X 0 N11 N3 T0 B4 MA1 N10 N2 Rsa B3 MA0 N9 N1 Rsb B2 LSB R/W = 0 N8 N0 OS B1 ACK ACK ACK (L) ACK (L) ACK (L)
X :DON'T CARE ACK :Acknowledged (L) :Latch and transfer timing
B) READ MODE
MSB 1 2 Address Byte Status Byte 1 POR 1 FL 0 1 0 1 0 1 MA1 1 MA0 1 LSB R/W=1 1 ACK -
ACK :Acknowledged
DATA SPECIFICATIONS
MA1, MA0 : programmable hardware address bits MA1 0 0 1 1 MA0 0 1 0 1 ADDRESS PIN APPLIED VOLTAGE 0 to 0.1Vcc to 0.3Vcc
OPEN or 0.2Vcc 0.4Vcc 0.9Vcc to to
0.6Vcc Vcc
N14 - N0 : programmable counter data CP : charge pump output current setting [0] : + 55 A (typ.) [1] : + 250 A (typ.) T2, T1, T0 : test mode setting bits CHARACTERISTIC Normal operation OFF Charge-pump SINK SOURCE Reference signal output 1/2 counter divider output T2 0 0 1 1 1 1 T1 0 1 1 1 0 0 T0 X X 0 1 0 1 Charge pump is OFF Only charge pump sink current is ON Only charge pump source current is ON Reference signal output 1/2 counter output NOTE (check output: NF) (check output: NF) (check output: NF) (check output: Band 4) (check output: Band 2)
X :DON'T CARE Note 6: Testing of the counter divider output requires the input of programmable counter data.
13
2004/11/24
TA1384FNG
Rsa, Rsb: Reference frequency divider ratio select bit. Rsa 1 0 X Rsb 1 1 1 DIVIDER RATIO 1/256 1/512 1/320 COMPARE FREQUENCY 15.265kHz 7.8125kHz 12.5kHz STEP FREQUENCY 62.5kHz 31.25kHz 50kHz
OS: tuning amplifier control bit [0] : tuning amplifier ON (normal operation) [1] : tuning amplifier OFF (charge pump is sink mode) B4, B3, B2, B1: Band output port control and band change control bit [0] : band output driver ON [1] : band output driver OFF
Band VHF Band VHF Band UHF Band B4 X X X B3 X X X B2 0 1 0 B1 1 0 0
When the bandswitch data is [1] for either B1 or B2, VHF mode is effective. When the bandswitch data is [0] for both B1 and B2, UHF mode is effective. POR: power-on reset flag [0] : normal operation [1] : reset operation FL: lock detect flag [0] : unlocked [1] : locked X : don't care
-EXAMPLE OF BUS DATA TRANSMITTERS: Start ADR: Address Byte DIV1: Divider Byte 1 (frequency data) DIV2: Divider Byte 2 (frequency data) CONT: Control Byte BAND: Bandswitch Byte A: Acknowledge P: Stop [1] Transmitter - 1 S ADR [2] Transmitter - 2 S ADR
A
DIV1
A
DIV2
A
CONT
A
BAND
A
P
A
CONT
A
BAND
A
DIV1
A
DIV2
A
P
[3] Transmitter - 3 (This can be applied if control data and bandswitch data have already been programmed.) S ADR A DIV1 A DIV2 A P [4] Transmitter - 4 (This can be applied if frequency data have already been programmed.) S ADR A CONT A BAND A P [5] Transmitter - 5 (This can be applied if frequency counter data and bandswitch data have already been programmed.) S ADR A CONT A P Until the IC-bus STOP condition is detected, it is possible to input the additional data without transmitting the address data again. (For example: Frequency sweep is possible with additional frequency data.) If data transmission is aborted, data programmed before the abort are valid.
14
2004/11/24
TA1384FNG TEST CIRCUIT 1
Vcc(5V)
*X'tal
Xo extl 51 0.1uF
A
Icc 1000pF
XtR
18pF
N.C.
N.C.
0.1uF
N.C.
N.C.
N.C.
N.C.
N.C.
24
23
22
21
20
19
18
17
16
15
14
13
DIVIDER 1/2 1/4
1/32 1/33 PHASE COMPARATOR
PROGRAMABLE DIVIDER B1 BAND SW UV
DATA INTERFACE
BAND DRIVER ADR B2
1
100
2
100
3
4
5
6
7
8
9
10
11
2200pF
12
2200pF
SCL
SDA
ADR
A
IBD
V
VBDsat
*X'tal: 4MHz (NDK:AT-51)
15
2004/11/24
TA1384FNG TEST CIRCUIT 2
Vt(33V)
33k
33k 0.01uF 2200pF 2200pF 2200pF L2 22k 33k
VL
1.5k
VH
1.5k
56pF 33k
2.7k
Vcc(5V)
1SS241 2200pF L1 5pF
2200pF
1000pF
IF out 20k
1SV262 7pF L3 0.1uF 10pF 10pF
L4
33k 100
18pF *X'tal
2200pF
0.047uF
10pF
5pF
24
23
22
100pF
21
20
19
18
17
16
15
14
DIVIDER 1/2 1/4
1/32 1/33 PHASE COMPARATOR
PROGRAMABLE DIVIDER B1 BAND SW UV
DATA INTERFACE
ADR
BAND DRIVER B2
1
100
2
100
3
4
5
6
7
8
1k
9
L5
10
11
2200pF
33
13
12
2200pF UHF in
33pF
SCL
SDA
ADR
100
1000pF
33pF
VHF in
L1 : 0.4mmd, 2.5mm , 6.5t L2 : 0.4mmd, 2.5mm , 2.5t L3 : 0.4mmd, 2.5mm , 2.5t L4 : 0.4mmd, 1.5mm , 1.5t L5 : TOKO (886BNF-0357) *X'tal: 4MHz (NDK:AT-51)
Measurement bus data setting Charge pump: High [250 A (typ.)] Frequency step: 62.5 kHz
16
2004/11/24
10pF
82pF 1SV262
TA1384FNG
TEST CIRCUIT 3
Noise Figure Meter out 11 or 12 DUT Noise Source 20 75-50 Impedance Transformer in
Figure 2: Noise Figure measurement
TEST CIRCUIT 4
fd Signal Generator 1 11 or 12 DUT 20 75-50 Impedance Transformer in Spectrum Analyzer
Signal Generator 2 fud
Figure 3: CM / IM3 / 6-ch beat measurement
17
2004/11/24
TA1384FNG I2C BUS CONTROL SUMMARY Data transmission format
S Slave address 7 bit MSB MSB 0A Data 8 bit MSB A Data 8 bit AP
S: Start condition P: Stop condition A: Acknowledge (1) Start / stop conditions
Serial data
Serial clock S Start condition P Stop condition
(2)
Bit transfer
Serial data
Serial clock
Serial data unchanged. Serial data can be changed.
(3)
Acknowledge
High impedance
Serial data from master device Serial data from slave device Serial clock from master device S High impedance
1
8
9
(4)
Slave address
A6 1
A5 1
A4 0
A3 0
A2 0
A1
A0
R/W 0
*
*
18
2004/11/24
TA1384FNG PACKAGE DIMENSIONS
Weight: 0.09 g (typ.)
19
2004/11/24
TA1384FNG HANDLING PRECAUTIONS
1. The device should not be inserted into or removed from the test apparatus while the voltage is being applied; otherwise breakdown or deterioration in performance of the device may result. Also, avoid any abrupt increasing or decreasing of the voltage. Overshoot or chattering of the power supply may cause the IC to be degraded. To avoid this problem, equip the power supply line with filters.
2. The peripheral circuits described in this datasheet are given only as system examples for evaluating the performance of the device. Toshiba neither recommend the configuration or related values of the peripheral circuits nor intend to manufacture such application systems in large quantities. Please note that the high-frequency characteristics of the device may vary depending on the external components, mounting method and other factors relating to the application design. Therefore it is the responsibility of users incorporating the device into their designs to evaluate the characteristics of application circuits. Toshiba only guarantee the quality and characteristics of the device as described in this datasheet and do not assume any responsibility for the customer's application design.
3. In order better to understand the quality and reliability of Toshiba semiconductor products and to incorporate them into designs in an appropriate manner, please refer to the latest Semiconductor Reliability Handbook (Integrated Circuits) published by Toshiba Semiconductor Company. The handbook can also be viewed online at `' http://www.semicon.toshiba.co.jp/ ''
20
2004/11/24
TA1384FNG Solderability
Regarding solderability, the following conditions have been confirmed. (1) Use of Sn-63Pb solder bath Solder bath temperature = 230(C degree C
Dipping time = 5 seconds The number Number of times = once
(2) Use of R-type flux Use of Sn-3.0Ag-0.5Cu solder bath Solder bath temperature = 245C Dipping time = 5 seconds Number of times = once Use of R-type flux
21
2004/11/24
TA1384FNG
RESTRICTIONS ON PRODUCT USE
The information contained herein is subject to change without notice.
030619EBA
The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. The products described in this document are subject to the foreign exchange and foreign trade laws. TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations.
22
2004/11/24

▲Up To Search▲

Price & Availability of TA1384FNG

	To Download TA1384FNG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .